Compilation Techniques for Reconfigurable Architectures
| Author | : | |
| Rating | : | 4.65 (654 Votes) |
| Asin | : | 144193510X |
| Format Type | : | paperback |
| Number of Pages | : | 223 Pages |
| Publish Date | : | 2014-01-07 |
| Language | : | English |
DESCRIPTION:
An introduction to hardware compilation and reconfigurable computing architectures, this book presents a variety of compiler code transformations and mapping techniques focusing on imperative programming languages.
So much to say wiredweird and so few pages to say it!Let's start by identifying the successful reader. If you can draw a clear, crisp line between hardware and software, then you're not that reader. Instead, you have passing knowledge of VHDL or Verilog, you know what SSA means in compiler-speak, and your first thought about a compiler is the intermediate tree, not lex/yacc or "version of the instruction set."If that's you, this book is really the best I know - which doesn't say a lot. The best parts of this bring out issues like gate vs cycle optimization, resource sharing, the merits of inlining and outlining, and the many issues of datapath
While many of these transformations and mapping techniques have been developed in the context of compilation for traditional architectures and high-level synthesis, their application to reconfigurable architectures poses a whole new set of challenges- particularly when targeting fine-grained reconfigurable architectures such as contemporary Field-Programmable Gate-Arrays (FPGAs).Organized in eight chapters, this book provides a helpful structure for practitioners and graduate students in the area of computer science and electrical and computer engineering to effectively map computations to reconfigurable architectures. Allows the reader to bridge the gap between the software compilation and the hardware compilation and synthesis domains. From the Back CoverThis book describes a wide range of code transformations and mapping technique